1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and specifically to a method of manufacturing a semiconductor device that forms wirings of a uniform height after polishing in a damascene wiring process using a plating method.
2. Description of the Related Art
In recent years, the miniaturization of wirings and the production of multi-layer wiring have been progressed accompanying the higher integration of semiconductor devices and the size reduction of semiconductor chips, and as a method for forming a multi-layer wiring structure, there has generally been used a process known as the damascene process, wherein Cu, which is a wiring material, is simultaneously or sequentially buried in via holes and wiring-trench patterns through a Cu seed layer using an electroplating method, and planarized using CMP (chemical mechanical polishing) method to form wirings.
The generally used damascene process will be described referring to the drawings. FIG. 6 is a sectional process diagram showing the procedures of a conventional damascene process. First, as FIG. 6 (a) shows, a barrier metal layer 7 and a Cu seed layer 8 are sequentially formed in wiring-trench pattern 6 opened in an etching-stop film 10 and an interlayer insulating film 5 formed on a semiconductor substrate 4.
Next, as FIG. 6 (b) shows, a Cu plating layer 9 is formed until the wiring-trench pattern 6 is sufficiently buried using an electroplating method. Next, as FIG. 6 (c) shows, the surface is planarized until the interlayer insulating film 5 is exposed using a CMP method to form damascene wirings.
Here, the reaction involved in the electroplating method will be described referring to FIG. 7. In the damascene process, a plating bath containing a suppressor 15, a brightener 16 and the like is used to bury fine patterns free of voids. The suppressor 15 has an effect to suppress the growth of plating, and an effect to densify the plating film. On the other hand, the brightener 16 has an effect to accelerate the growth of plating. As FIG. 7 (a) shows, since the brightener 16 evenly adsorbed in the initial stage of growth is retained on the adsorbing surface, in the state of FIG. 7 (b) wherein the growth of the Cu plating layer 9 has been progressed, a concentration gradient is produced on the surface. This concentration gradient causes the growing reaction called bottom up wherein the growth of the bottom of the wiring-trench pattern 6 is accelerated. As FIG. 7 (a) shows, since the diffusion coefficient of the suppressor 15 is small, the concentration on the surface is higher than the concentration in the wiring-trench pattern 6, and the growth of plating on the planarized area is suppressed to assist the bottom-up effect. However, since the concentration gradient of the brightener 16 as described above is sustained even after the wiring-trench pattern 6 is filled with the wiring material, the area on the wiring-trench pattern 6 is protruded as FIG. 7 (c) shows. On the other hand, since the content gradient of the brightener 16 as described above little occurs in a wiring trench having a sufficient width, the area on the wiring-trench pattern 6 is not protruded (refer to FIG. 6 (b)).
As described above, the protrusion of the plating film occurs on fine patterns, due to the effect of the additives used for filling fine patterns without forming voids. Therefore, in the CMP process shown in FIG. 6 (c), since a long polishing time is used for completely polishing Cu on the interlayer insulating film 3 including excessive Cu protrusion due to bottom up, the costs of the CMP process increase, and erosion 13 or dishing 14 due to polishing is caused to produce variation in the wiring height.
In the above-described Cu plating method using the conventional damascene process, it is essential to use a plating bath and plating conditions having bottom-up properties to fill fine patterns without producing voids. However, in the plating method having bottom-up properties, protrusions occur on the fine patterns. As conventional examples to use the multiple stages of current steps of Cu plating, U.S. Pat. No. 6,140,241 and U.S. Pat. No. 6,319,831B1 disclose a two-step method to switch the current steps from a low current to a high current, or to provide an idling step after the low-current step. However, since these methods cannot solve the problem of protrusions on fine patterns, erosion 13 and dishing 14 after CMP are unavoidable. Although U.S. Pat. No. 6,107,186 discloses that flat CMP can be performed by protruding the plating films of high pattern densities, the load to the CMP is large, and increase in CMP costs cannot be avoided.
U.S. Pat. No. 6,245,676B1 (Japanese Patent Laid-Open No. 11-238703) discloses that flat CMP can be performed by applying a reverse bias current for removing the molecules of the suppressor in the plating solution to relatively protrude the areas on wiring-trench patterns 6 compared to the flat areas. In this method also, the load to the CMP is large, and increase in CMP costs cannot be avoided, as in the above-described U.S. Pat. No. 6,107,186. Although Japanese Patent Laid-Open No. 2001-217208 discloses to apply a backward current after filling the wiring-trench patterns 6 using the forward current, no detailed conditions are disclosed. The patent also discloses that the repetitive applications of polarity-inversion pulses are effective; however, the effect on the reliability of the devices is not described. Although the conditions of applying forward current after applying backward current affect the reliability of the devices, no detailed conditions are described.
As described above, in the Cu electroplating method in the conventional Damascene process, in order to fill fine patterns without producing voids, it is essential to use a plating bath and plating conditions having bottom-up properties; however, since protrusions occur on the fine patterns in the plating method with bottom-up property, there has been demanded the development of the method to solve the problem of protrusions on the fine wiring patterns without changing the filling properties of the fine patterns or the quality of plating films.